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Nr.	Titel	Autor	Jahr
1	Impact of Dielectric Types on Surface Topography for Wafer-Level Hybrid Bonding	Dubey, Vikas* et al.	2024
2	Navigating Complex Process and Design Challenges in Hybrid Bonding for Advanced Semiconductor Integration: A Comprehensive Analysis	Dubey, Vikas* et al.	2024
3	Automatic Detection of Via Arrays in AFM Images for CMP Dishing Evaluation	Zienert, Andreas* et al.	2023
4	Impact of Dielectric and Copper Via Design on Wafer-to-Wafer Hybrid Bonding	Dubey, Vikas* et al.	2023
5	Towards knowledge-enhanced process models for semiconductor fabrication	Rothe, Tom et al.	2023
6	A Hybrid Chemical Mechanical Planarization (CMP) Model for Time-Dependent, Spatial Material Removal Rate Optimization	Rothe, Tom* et al.	2022
7	Automatic Analysis of CMP Dishing in Via Arrays from AFM Images	Langer, Jan* et al.	2022
8	The BDRIE-HS* Technology Approach for Tiny Motion Detection with Improved Sensitivity and Noise Performance	Forke, Roman et al.	2022
9	3D Wafer Level Packaging By Using Cu-Through Silicon Vias For Thin Mems Accelerometer Packages	Hofmann, Lutz et al.	2017
10	3D integration approaches for MEMS and CMOS sensors based on a Cu through-silicon-via technology and wafer level bonding	Hofmann, Lutz et al.	2015
11	SIMEIT-Project: High Precision Inertial Sensor Integration on a Modular 3D-Interposer Platform	Steller, Wolfram et al.	2014
12	Investigations on partially filled HAR TSVs for MEMS applications	Hofmann, Lutz et al.	2013
13	Technologieentwicklung für optimiertes MEMS Packaging durch Si-TSV-Rückseitenkontaktierung	Meinecke, Christoph et al.	2013
14	TSVs mit hohem Aspektverhältnis und Kupfer-Bonden für MEMS	Hofmann, Lutz et al.	2013
15	Vertical Integration techniques for MEMS using HAR TSV	Hofmann, Lutz et al.	2013
16	CMP issues arising from novel materials and concepts in the BEOL of advanced Microelectronic Devices	Gottfried, Knut et al.	2007

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